Asynchronous counting devices



March 21, 1967 Filed April 23, 1963 G. R. COGAR ASYNCHRONOUS COUNTINGDEVICES 8 Sheets-Sheet l PRECLEAR (P05 DURING CL) 2 ENPUT SECTION I L..L J.

OUTPUT SECTION INVENTOR GEORGE R. COGAR CONTROL SECTEON! ATTORNEY arch21, 1967 G. R. COGAR ASYNCHRONOUS COUNTING DEVICES a Sheets-Shet 4 FiledApril 23, 1965 o 0 3 S E G A T S O PRECLEAR (P08 DURING CL) 1967 G. R.COGAR 3,310,660

ASYNCHRONOUS COUNTING DEVICES Filed April 25, 1963 a Sheets-Sheet sFraser FIG 8b FIG. 8

FIG. 8b

arch 1967 G. R. COGAF! 3,310,660

ASYNCHRONOUS COUNTING DEVICES Filed April 23, 1963 a Sheets-Sheet 6 I II I I 1 I I s United States Patent 3,310,660 ASYNCEilRONOUS COUNTINGDEVICES George R. Cogar, Doylestown, Pa., assignor to perry RandCorporation, Detroit, Mich, a corporation of Delaware Filed Apr. 23,1963, Ser. No. 275,000

9 Claims. (Cl. 235-92) This invention relates to counting systems andmore particularly to delay-free asynchronous counting arrangements.

With the wide acceptance and use of electronic com puting devices anddata processing systems, faster and faster computing devices must bedevised to. meet the requirements of the ever increasing problemcomplexity and the problem of reduction and handling of large masses ofinformation. Heretofore, increases in the speed of the overall system orcomputer operation have come from increasing the speed of operation ofthe relative parts and components of the data processing system orcomputer. For example, by increasing the speed of operation of thearithmetic components of the computer, it is possible to increase theoverall speed of such a computer. However,

certain limitations upon the speed of operation which such devices mayattain are inherent in the particular manner of operation which mostpresent computers and data processing systems employ. of synchronousoperation, that is, the computer operates on a distinct time cyclewherein each particular bit of information and each group of informationbits forming a computer word occupies a well-defined time period. Themachine is thus limited in its operation to an inflexible repetitivetime cycle equal to some multiple of the originally chosen word lengthor vice versa. Once the particular clock sequence and frequency arechosen, all operations within the computer, such as the transfer ofdata, arithmetic computation on data and manipulation of data iscontrolled by the timing selected. Provisions to allow for variations ofthe timing cycles involve complex equipment and programming techniques.Further, since these time intervals are preset and pre-assigned, theymust be arranged to provide for the worst possible conditions which mayoccur due to individual operations within the machine. Thus, becausecertain elements within the machine are slow to react, that is, theytake a long time to settle down to a stable operating condition, thetime period provided must be sufficiently long to allow these slowerelements to react. However, during this longer period many of theremaining elements within the computer are already settled to a reliableoperating condition long before the slower operating component is readyto produce error-free information. Further, in synchronous operations,each step of the transfer of information from one particular componentto the next is controlled by individual clocking pulses. Therefore, ifeach stage is to be timed according to the worst possible conditionwhich might occur within the computer, then the stages of unnecessarydelay are compounded one upon another, thus producing a time sequencewhich is far slower than that required to operate most of the componentswithin the machine. Consider, the time spent in certain arithmeticoperations-for example, the time required to propagate a carry from thelowest order to the highest order. Though this type of carry may rarelyoccur, sufficient time must nonetheless be allowed for the possibilityof this particular carry. This must be done to prevent the loss ofthis'carry, which would produce an incorrect result if not accountedfor. Thus, it can be seen that with machines of the synchronous type, alarge portion of the timing cycle is wasted to provide for conditionswhich,

The procedure employed is that i ice although infrequent in theiroccurrence, must nonetheless be considered, if error-free information isto be obtained. Hence, these systems may not be flexible enough to enable them to meet the needs of the problem presented for solution.

One solution to the foregoing problem, which would permit the moreelfetcive utilization of the time available for computation and permitmore flexible use of time, would be the use of an asynchronous type ofcomputing and data processing device. The asynchronous device, ascontrasted with the synchronous device mentioned above, does not requirea clock or timing pulse for its operation. Instead the asynchronousdevice determines each indi-' vidual operation and the time at which itis to begin depending upon the arrival of all information necessary forthe operation. Stated another way, an asynchronous machine depends forits operation upon all necessary inputs being available to a particularstage before that stage will operate. It is generally a level type ofmachine rather than a pulse type machine; i.e., in an'asynchronousmachine the signals which are made available in the various stagesthereof are as voltage levels rather than short voltage pulses as isfrequently found in synchronous types of computing devices. In thismanner, the inputs necessary for the operation of a particular stage areavailable sufficiently long to permit all the necessary inputs to arriveand to be present'for operation of the stage. The in dividual stages ofthe computer operate as soon as the data required for that particularstage has arrived and there is no need to wait for the arrival of aparticular clock pulse which may occur long after the arrival of allnecessary input signals. Word lengths and word formats may be variedbecause of the independence of the information from a rigid clock, thuspermitting a more flexible manner of operation.

Briefly stated, the embodiments of the invention described consist oflevel operating asynchronous counting arrangements which operateindependently of clock pulses. Operation of these devices depend solelyupon the presence or absence of voltage levels or signals from inputsources as well as from certain stages within the device itself. A firstembodiment describes an asynchronous counter capable of counting in themodulo two number system. The device consists of two substages, eachcomposed of a number of gates which operate in conjunction with theinput signal to control the response of the individual substages toinput signals. For example, the first substage may be made responsive tothe first input signal to effect a first count. The device in accordancewith the levels developed within the first substage permits the secondsignal to be counted by the second substage and prevents the firstsubstage from responding to such a signal. After receipt of the secondsignal, the device will prepare the first stage to respond to the nextarriving signal to be counted, hereinafter called the count signal. Thissequence of steps will continue back and forth between the two substagesas each successive count signal arrives. v v

In a further embodiment, three substages are provided to form anasynchronous counting device counting according to a modulo threenumbering system. The internal connections of the various substagespermit the device to operate so as to permit the first substage torespond to a first count signal, the second substage to respond ,to thesecond count signal and the third substage to respond to the final orthird count signal. The device then by its own internal levels controlsthe recycling of-the device to respond to the next group of threepulses. In this manner, the device is free to operate at a speed to bedetermined by the availability of the output levels of the gates whichcompose the various substages. The individual stages of the modulo twoor modulo three counting devices may then be cascaded to form largercounting chains with proper arrangements made for carrys between thestages, as shown by further embodiments of the device. Further, theembodiments described serve to teach a procedure whereby the systemsshown for the modulo two and modulo three counting systems may beextended to include counting systems of any modulo n.

It is, therefore, an object of this invention to provide an improvedcounting device.

It is an object of this invention to provide an improved form ofasynchronous counting device.

vIt is a further object of this invention to provide an improved form ofmodulo two asynchronous counting device.

It is a further object of this invention to provide an improved form ofasynchronous modulo three counting device.

It is yet another object of this invention to provide an improved formof asynchronous counting device operating independent of a clock ortiming signal and dependent upon the levels of the signals within saidcounting device, as well as its input signals.

It is yet another object of this invention to provide a multi-stageasynchronous modulo two counting device capable of operating atincreased speed and indepndent of any form of clocking or timing signalsource.

It is still a further object of this invention to provide an improvedform of multi-stage asynchronous modulo three counting device whichoperates independent of any clocking or timing signal source anddependent solely upon the signals present within said device, as well asits input signals.

It is still a further object of this invention to provide an N stageasynchronous counting device capable of operating within the modulo Nnumbering system which operates independent of any clocking or timingsignal source and solely dependent upon the signal levels within saiddevice, as well as its input signals.

It is yet another object of this invention to teach a method by whichasynchronous counting devices may be constructed to operate in anymodulo N numbering system and which operate independent of any timing orclock source and which operate solely dependent upon the signalsavaliable within said device, as well as its input signals.

It is still another object of this invention to provide a device capableof handling information without necessity of providing a fixed or rigidclock or timing signal arrangement.

Other objects and features of the invention will be pointed out in thefollowing description and claims and illustrated in the accompanyingdrawings which disclose by way of example, the principles of theinvention and the best modes which have been contemplated for carryingthem out.

In the drawings:

FIGURE 1 illustrates a single stage of an asynchronous counting deviceconstructed in accordance with the principles of the invention andarranged to count in a modulo two numbering system;

FIGURE 2 is a table indicating the various section outputs of the deviceof FIGURE 1;

FIGURE 3 illustrates a multi-stage asynchronous counting device arrangedto count in the modulo two numbering system and further illustrates analternative arrangement of the counting device whereby the output signalpattern of the various stages may be modified;

FIGURE 4 is a table indicating the various section outputs for thedeviceas shown in FIGURE 3 in the first arrangement;

FIGURE 5 is a table indicating the various section outputs for thealternative arrangement of FIGURE 3;

FIGURE 6 illustrates a signal stage of an asynchronous counting deviceconstructed in accordance with the principles of the invention andarranged to count in a modulo three numbering system;

FIGURE 7 is a table indicating the various section outputs of thecounting device illustrated in FIGURE 6;

FIGURES 8a and 8b illustrate a multi-stage asynchronous counting deviceconstructed to operate in the modulo three counting system. FIGURES 8aand 8b are to be viewed as shown in FIGURE 8;

FIGURE 9 is a table indicating the various section outputs of thecounting device as shown in FIGURES 8a and 8b; and

FIGURE 10 is a table indicating the various section outputs of thecounting device shown in FIGURES 8a and 8b in its alternativearrangement.

Similar elements are given similar reference characters in each of thedrawings.

Referring to FIGURE 1, there is shown a single stage of an asynchronouscounting device constructed in accordance with the principles of thisinvention and arranged to count in the modulo two numbering system. Thedevice consists of two substages S52 and SS4, respectively, eachsubstage further being composed of a number of individual sectionsgenerally described as the input section, the output section and thecontrol section. The input sections of the various substages aredesignated A, the output sections are designated B and the controlsections are designated C. The sections of the first substage SS2 and ofthe second substage SS4 are distinguished from one another by the use ofthe prime for all sections of the second substage SS4- Therefore, theinput section of the second substage SS4 will be defined as A, theoutput section as B, and the control section as C. Each of the sectionsfor the various substages include negative input And-inverter gateswhich produce a positive or high signal at its output if all its inputsare present and negative, whereas a negative or low signal is producedat its output if any of its inputs are positive or high.

More specifically, tie operation of the And-inverter circuits may beunderstood by considering the two input And-inverter gate C of thecontrol section of substage SS2. As can be seen from FIGURE 1, theinputs are introduced to the anodes to two diodes C and C arranged as anAnd gate. The cathodes of diodes C and C are connected to a commonnegative bias source via a resistor 10. The And gate output, taken fromthe cathodes ofthe diodes C and C is connected to the base of a PNPtransistor 12 which is arranged in a grounded emitter configuration. Theoutput for the gate output is taken from the collector of the transistor12. The collector of the transistor 12 is also biased negatively througha resistor 14. When negative pulses exceeding the bias voltage areapplied to both of the diodes C and C of the gate C, no current ispermitted to flow within the diode arrangement and the voltage presentedto the base of the transistor 12 is, neglecting any loss due to the biasresistor 10, the negative value of the bias supply itself. If the valueof the negative bias supplied to the collector of the transistor 12 islarger, that is negative with respect to the value of the negativesignal now applied to the base of the transistor 12, the transistor 12will be permitted to conduct thereby providing an output level which isthe ground value of the emitter. that the signals are represented as azero voltage for a positive signal and a 3 volt signal for a negativesignal, the production of a Zero or ground level at the output of thecollector of the transistor 12 is equivalent to production of a onesignal. Thus the introduction of two negative inputs has produced'asingle positive output. The introduction of a single negative and asingle positive to the respective diode-s C and C of the gate C willproduce the following effects: The positive signal on, for example,diode C will cause a current to flow in diode C whereby the level of thejunction point at the cathodes of the two diodes rises to that of groundor the positive value applied. This positive value will Assuming then beapplied .to the base of the transistor 12 pre venting it fromconducting. This is due to the fact that the base of the PNP transistor12 is now positive with respect to the emitter, rather than negative asrequired for conduction. With the transistor prevented from conducting,the output signal produced is due to the negative bias voltage on thecollector of the transistor 12. Thus, for a single positive and a singlenegative input, a negative signal will be produced. In a similarfashion, if both of the input signals to the diodes C and C of the gateC were positive, the current permitted to fiow through the respectivediodes C and C would produce a positive signal at the base of .thetransistor 12. Hence, the transistor would not conduct, resulting in theproduction of a negative output voltage at the collector.

Turning now to FIGURE 1 as a whole it can be seen that gate A of theinput section, is constructed of three diodes designated A1, A2, and A3arranged with their cathodes connected to a resistor and negative biassource. The anodes of the diodes A1, A2 and A3 are arranged to receiveinput levels according to the input information and control which isnecessary for proper operation. The output from the common cathodes ofthe diodes A1, A2 and A3 are connected by the lead 16 to the base of aPNP transistor TA arranged in a grounded emitter configuration. Thecollector of the transistor TA is connected through a suitable resistorto a negative bias supply. The diode A1 receives an input which isthe'output of the transistor =12 of the gate C in its own substage. Thediode A2 receives an input from the count signal line 18 via theconnecting line 20. The diode A3 receives asan input the output signalof the gate A in the input section of the second substage.

The B gate of the output section of the first substage is similar inconstruction to that described with reference to the A gate of the inputsection but employs only two diodes in the And portion. The inputs tothis gate are as follows: diode B1 receives the output of the A gatealong the line 24, while the diode B2 receives as its input the outputof the B gate of the output section of substage SS4 along the line 26.

The C gate of the control section of the first substage is composed oftwo diodes with suitable bias supply and an output transistorarrangement as described with reference to the other gates A and B. Theinputs to its diodes C1 and C2 are as follows: diode C1 receives as itsinput the output of the A gate of the input section of its own substagevia the line 28 while the diode C2 receives as its input the output fromthe B gate of the output section of the same substage via the line 30.Thus, it is obvious that the control gate C receives its inputs basedupon the outputs of its own input and output sections and in turnproduces an output from its output transistor to supply one of theinputs of the input section gate A. Thus, the ability of the controlsection gate C to control the input section gate A to respond to countsignals will be dependent upon the output of the input section gate Aand the output section gate B,

In that the inputs to the gates A and B of the substage are alsodetermined by the outputs of the gates A and B of the second substagethe inputs to the control stage C will be derived depending upon thevarious available conditions within the entire stage S1 composed of bothsubstage SS2 and SS4. As will be made more clear from the descirptionbelow, the various steps of operation of the asynchronous device willdepend upon the input signals available as well as the outputs of thevarious component gates which compose a particular stage. Further when aplurality of these stages are cascaded, the operation of each stage willdepend then upon the component gates within the stage as well as theoutputs of the stages before it in the counting device.

The gate A of thesecond substage SS4 is similar in construction to thegate A of the first substage SS2. It

receives at its diodes Al, A2, and A3 inputs which cor respond to: 1)the output of the gate A of the first substage SS2 via line 32; (2) thecount input signal from the line 18 via the connecting line 22 andfinally; (3) the output of the gate C which is the control section ofthe second substage SS4 via line 34.

The B gate which is the output section gate for the second substage SS4is similar in construction to the B gate of the first substage SS2 withthe addition, however, of a further diode. This additional diode B3receives a preclear pulse, via line 36 to allow this gate to be set toan initial condition as will be described below. The preclear pulse willbe positive during clearing intervals and will return to a negativevalue at which it will remain for the entire operation. The diode Bl isconnected via a line 38 to the output of the gate B of the substage SS2.In this manner the diode B'1 receives an input commensurate with theoutput of the gate B. Diode B2 is supplied with an input via line 40from the output of the gate A of the same substage SS4.

The control section gate C is similar in construction and arrangement tothe gate C of substage SS2. At diode Cl it receives the output of the Bgate of its own substage via line 42 while at diode C2 it receives theoutput of the A input section gate of its own substage SS4 via the line44. Thus as was the case with the gate C, the gate C is made responsiveto the output of the input section gate, A and the output section gateB. The output of this g ate as described above will be conducted alongline 34 to the diode A3 of the gate A to control the respouse of thisgate to count signals.

The operation of this single stage modulo 2 counting device will now beconsidered with reference to FIG- URES 1 and 2. FIGURE 1 illustrates theconstruction of the stage, whereas FIGURE 2 describes the output signalsavailable at the various gates of the stage. Input count signals areintroduced via line 18 and thence over the lines 20 and 22 to the inputgates A and A of the substages SS2 and SS4, respectively. The countsignal is represented as a negative potential on the line 18 for theentire count signal period. At the termination of the count period theline 18 is returned to a positive potential, which persists at all timesexcept the count period. The count signal introduced on the line 18 willthen be passed through one or the other of the input gates A or Adepending upon the condition of the control gates C and C of therespective substages. Due to the manner of interconnection, only one ofthese control section gates will control its respective associated inputgate to respond to the count signal. The other control gate will causeits associated input section to be ineffective to respond to the inputsignal. During the following input cycle, the gates Will reverse theirfunctions so that the input section which was blocked when the firstinput signal was applied will be allowed to respond to the second inputsignal whereas that gate which was permitted to respond to the firstinput signal will be blocked from responding to the second count signal.This alternative arrangement will continue on all subsequent inputsignals and will cause the first substage SS2 to respond to all oddsignals whereas the second substage SS4 will respond to all even countsignals in a manner described below.

Prior to the receipt of any count signal on the line 18 the preclearsignal will be placed on the line 36. As has been explained above, thepreclear line is maintained at a negative potential during all timesexcept the preclear cycle itself. It is during the preclear cycle thatthe preclear line 36 has placed upon it a positive potential to effectthe clearing operation and to place the device in its initial countcondition. Assuming now that the device is to be employed in a countingoperation, the preclear signal is applied and will cause the followinggate outputs :to be produced: the positive preclear signal will place asignal upon the diode C1 and the diode B2. The count line 18, as wasdescribed above is maintained at a positive potential except during thecount signal period. Thus a positive input is placed at the diode A2 vialine 20 as well as the diode A2 via the line 22. The inputs to the diodeA2 and A2 will cause the outputs of the gates A and A to go negative.The negative output of the gate A will be impressed upon the diode B1,as well as the diode C1. The negative output signal of the gate A willbe impressed upon the diode B2 as well as the diode A3. The gate B ofthe output section of the substage SS2 now has negative inputs on bothof its diodes B1 and B2 causing the output of the gate B to go positive.The positive output signal of gate B is impressed upon the diodes C2 andB"1. The positive input to the diode Bl will not atfect the output ofthe gate B in that it is producing a negative out-put in response to thepositive preclear signal on diode B'3. However, the positive output ofthe gate B upon diode C2 will cause the gate C to produce a negativesignal which is carried over the output line 46 to diode A1 of the inputsection A. The gate C has received negative inputs on its diode C1 fromthe output of the gate B and on its diode C2 from the output of the gateA. Thus, the output of gate C will be a positive signal which is appliedvia the line 34 to the input diode A3. Accordingly, at the end of theapplication of the preclear signal the outputs of the various gates ofsur stage SS2 are as follows. The gate A output is negative; the outputof gate B is positive; the output of gate C is negative, whereas theoutputs of the gates of the substage SS4 are as follows: A negative;gate B negative; gate C positive. At the end of the preclear period whenthe preclear positive signal has been removed, the line 36 will returnto a negative value as was described above. This will cause the input tothe diode B3 to go negative but will have no effect as to the output ofthe gate B itself due to the presence of a positive signal on diode B'lkeeping the gate output negative. This state of outputs as describedwill continue until the application of the first count signal to theline 18.

The outputs of the gates of substages SS2 and SS4 are shown in the tableof FIGURE 2, in the first row marked preclear applied. appear in thecolumns headed A, B and C, whereas the gate outputs for substage SS4appear in the columns headed A, B and C. These output signals are shownfor the condition where the preclear signal has terminated and thenegative level is returned to the preclear line. The output of the Bgate is taken as the stage S1 output to indicate the count condition ofthe stage S1. A positive output signal will be employed to represent thezero or reset condition of the stage S1. The negative output signal willbe employed to represent the one or set condition of the stage S1. Theseoutput signals may be deteoted by means not shown to provide countindications to associated equipment. These detecting means may take theform of gates respectively responsive to the zero or one output signals.

As described above, the count signals are negative signals impressedupon the count signal line 18. The application of the first count signalwill place negative signal-s on the diodes A2 and A2. The inputs of thegate A are now all negative thus causing the gate to produce a positiveoutput signal. themselves are constructed in the negative inputAndinverter logic and will thus produce a positive output if all inputsare present and negative but will produce a negative output if any ofits inputs is positive. The positive output of the gate A is introducedvia line 24 to the diode B1 and further over the line 32 to the diodeA'l. As a result of the introduction of the positive input to theterminal diode B1 the output of the gate B will be changed from positiveto negative impressing a negative value on the diodes C2 and Bl. Thepositive output of the gate A is also conducted via line 28 to the diodeC1. The intro- The gate outputs for substage SS2 It should be recalledthat the gates duction of the negative signal to the diode B1 will causeall inputs of the gate B to be negative and thus produce a positiveoutput at the output of the gate B which in turn is impressed on thediode O1 and the diode B2. The positive input to diode B2 of the gate Bwill not affect its output and will remain negative. This is due to thepositive value already applied to diode B1 by gate A. However, theapplication of the positive signal to the diode C1 will cause the outputof the gate C to go from a positive value to a negative value. Thenegative output of the gate C is applied to the diode A3. Thus, at theend of the first negative count signal, the gates A, B and C produceoutputs which are positive, negative and negative respectively, whereasthe gates A, B and C produce outputs which are negative, positive andnegative respectively. These outputs are shown in the columns A, B, C,A, B and C in the row opposite the numeral 1 in FIG- URE 2.

In FIGURE 2 the outputs of each of the sections A, B, C of substage SS2and sections A, B, C of substage SS4 are arranged in columns for each ofthe conditions are shown in rows across the columns. In the row titledWhen Count Terminates following the row marked 1 the outputs representthe stable state of the device after the first count signal has beenreceived and the device has settled to its state preparatory to thereceipt of a further count signal. By checking the B output it isimrnediately evident that the device is now in its one count state. TheB output being negative, as stated above, indicates the device is in theone or set count condition. It is further possible to determine to countcondition of the stage S1, by looking simultaneously at the outputs ofboth substages SS2 and SS4, that is the outputs of output sections B andB. It can be seen that the B output is positive indicating a zero orreset condition for substage SS4 for the period following thetermination of the first count signal. It can further be seen that theoutput of section B was negative after the preclear signal was applied,indicating that substage SS4 was on during the period before the firstcount signal was applied. Thus if both the outputs B and B are detected,the zero condition of the stage S1 may be represented as B=0 and B=l,whereas the one condition of the stage S1 may be represented as B=1 andB=0.

Following the application of the negative count signal the count signalline 18 is returned to a positive value and impresses upon the diodes A2and A2 its positive level. The application of the positive signal to thediode A2 will cause the output of the gate A to go to a negative valueand apply the negative signal to the diodes B1, C1 and Al. The inputs ofthe gate C are now both negative causing its output to change to apositive value and impress a positive signal upon the diode A1. Thus,prior to the receipt of the next count signal, the gates A, B, and C arerespectively at negative, negative and positive values whereas the gatesA, B and C remain as they did during the application of the count pulseitself, that is producing negative, positive and negative outputsrespectively. It should be understood that a single positive input issufficient to cause a gate to produce a negative output and that furtherpositive inputs are ineffective to alter the output of such a gate.

If we now compare the outputs of the control gates C and C, it isobvious that the substage whose control section shows a negative outputsignal prior to the receipt of a count signal will be the substage whichwill respond to the next count signal. Thus, prior to the application ofthe first count signal the control gate C is caused by the preclearsignal and the positive level of the count line to produce a negativeoutput signal thus altering the first substage to respond to the firstcount signal. It can further be seen that the output of the control gateC is in the positive state and renders its input section gate A unableto respond to the first count signal. It should be noted at this timethat the gates employed will eifectively be locked out, that isprevented from responding to a particular input signal if any one of itsinputs are positive. This is true because a single positive input to agate will cause the gate to produce a negative output regardless of theother inputs which it receives. Therefore, if the control gate of aparticular substage puts positive level upon the associated input gateof that substage this gate is rendered unable to respond to the incomingcount signal. On the other hand, the application of a negative signal toa particular input section gate is effective to alert its associatedinput gate. In this manner, the application of a further signal from acount signal line may determine the output which an input gate willproduce. From the table of FIGURE 2 it can be seen that the output ofthe gate C is positive at the termination of the first count pulsewhereas the gate C is negative. Thus, it appears evident from the tablethat for the next incoming count signal, the substage SS2 will beblocked effectively by the positive output of the control gate C whereasthe input gate A of the second substage SS4 will be effective to respondto this count signal due to the negative output of its control gate C.It should also be noted, however, that as a result of the application ofthe first count pulse the output of the gate C goes from its positivevalue blocking the input section of its associated input section to anegative value which apparently would permit the count pulse to pass theinput section. However, the output of the gate A connected via the line32 to the diode A1 assures that the gate A will remain locked and unableto respond to the count signal.

The following count signal or second count signal applied to the countsignal line 18 causes the impression of a negative signal via the line20 to the diode A2 and via the line 22 to the diode A2. The count signalis not permitted to pass through the gate A due to the action of thepositive signal on the diode A1 as a result of the output of the controlgate C of its own substage. The count signal, however, is permitted topass the gate A whose other two inputs, that is the diodes A1 and A3 arenegative. It is obvious that a positive signal impressed upon the dodeof A2, causes the output of the gate A to become negative whereas theapplication of a further negative signal to the gate A'2 would result inthe gate producing a positive output. The application of the negativecount signal results in the output of the gate A going positive andapplying a positive value signal to the diodes B2, C=2 and A3. Thepostive value applied to the diode A3 will be ineffective to change theoutput of the gate A in that a positive input to the diode A1 is alreadycausing the gate to produce a negative output signal and the gate willnot respond to additional positive signals. The application of thepositive signal to the diode B2 causes the gate B to now produce anegative output signal which is impressed upon the diode C1., The outputof the gate C will remain negative despite the change in the inputs tothe diodes of the gate C in that the efiect of the changes in theoutputs of gates A and B is merely to interchange the former inputswhich existed on the diodes. The negative output of the gate B is alsoconducted via the line 26 to the input of diode B2 resulting in theproducing of a positive output signal by the gate B. This positivesignal is impressed upon the diode C2 as well as the diode B1. Thepositive input to the diode Bl is ineffective to change the output ofthe gate B due to the already existing positive signal from the gate Ato its diode B2. The positive signal from the gate B, however, appliedto the diode C2 is effective to change the output of the gate C to anegative value and thus apply a negative signal to the diode A1. Hence,during the interval that the second count signal is applied and aftersufiicient time has been allowed for various gates to settle downv totheir stable values the outputs of the gates A, B, and C will be foundto be negative, positive and negative respectively whereas the outputsof the gates A, B and C will be positive, negative and negativerespectively. These outputs are shown in FIGURE 2 in the row headed 2.

When the count signal terminates, a positive value is returned to theline 18 to cause application of a positive value to the diodes A2 andA2. The positive signal will change the output of the gate A in that oneof the negative inputs has been removed and replaced by a positivesignal. The output of the gate A will become negative and impress anegative voltage upon the diodes BZ, C2 and A3. The negative output ofthe gate A will be efiective to change the output of the gate C from anegative value to a positive value in that both inputs of the gate C nowreceive negative input signals. The positive output of the gate C willbe applied to the diode A3 of gate A. Thus at the termination of thecount pulse and during the positive level period which follows, thegates A, B and C are found to remain in the states in which they existedduring the receipt of the second count pulse itself,

that is with output values of negative, positive and negative,respectively for the gates A, B and C whereas the gates A, B and C nowproduce outputs which are negative, negative and positive respectively.These outputs are illustrated in FIGURE 2 in the row headed When CountTerminates following the row 2. Thus, prior to the receipt of the thirdinput signal the second substage is once more locked out and the firstsubstage is made ready or alerted to respond to the third input countsignal. This toggling operation, whereby the first substage is unlockedfor all odd signals and the second substange is unlocked for all evensignals, will continue for the entire count operation. It will furtherbe observed that the operation of the control section itself isdependent upon the particular outputs of its own input and outputsection. Thus upon receipt of a count signal by a particular substage,the input and output sections are able to control the control section toprevent response to the following count signal by the same substage, butwill permit the other substage to receive said signals. It can furtherbe seen that the input and output sections of both substages areinterconnected to sense each others respective outputs. This aids in thedetermination of which substage has responded to an input, and permitsthe lockoutalerting arrangement described. It is due to this internallycontrolled lockout-alerting arrangement that the device is able tooperate at speeds in excess of that which are normally obtainable withsynchronous devices. The counting device is permitted to lock and unlockits respective input gates at a rate determined by the availability ofinputs and output signals within the device itself. :It does not requirethe use or application of external clocking or timing signals todetermine the repetitive rate at which this device may operate. Eachgate is permitted to operate as soon as its respective inputs areavailable. The only requirement for the repetition rate of the inputcount signals is that it be sufiiciently low to permit the device toachieve a stable condition between successive inputs.

FIGURE 3 illustrates the manner in which a number of the stages ofFIGURE 1 may be connected together to form a multi-stage modulo 2counting chain. It is evident from the drawings of FIGURE 3 that therespective stages S and S200 are the same as that illustrated withrespect to FIGURE 1. The stage S100 receives its input count signals vialine 18 as in FIGURE 1. Each succeeding stage as illustrated by stageS200 receives its input from the output section B of the first substageS8102. Thus each time the first substage S8102 produces an outputsignal, a signal will be transmitted to stage S200 via the line 50. Thesignal will be passed to the terminal point 52 through the Switchblade54, which is in the upper closed position for the first embodimentdepicted, to the input count line 18 of stage S200. For example, whenthe first count signal arrives, the substage $8102 of stage S100produces a negative output signal which will result in the setting ofsubstage 202 of stage S8102 and S8202 of the stages S100 and S200 willassume the one count state. The following count signal will cause thesecond substage, that is substage S5104 of stage S100 to be in the countposition, but substage SS202 of stage S200 will remain in the same countposition. The count state of substage 202 is due to the fact that theoutput signal at the output stage B of substage S8102 of stage S100 ispositive during the entire time of the second count pulse and isineffective to cause the stage S200 to count. Upon the application ofthe third count signal via the line 10, the substage S8102 of stage 5100would respond to the third count pulse and produce a negative outputsignal which will cause the stage S200 to also count. The countingoperation will continue in this manner whereby each time substage SS102of stage S100 receives a count signal, a signal will be passed to stageS200 to permit it to count. The counting pattern for this two-stagemodulo 2 counting device is illustrated in Table I below whereas theoutputs of the various gates are shown in FIGURE 4.

TABLE I Count Signal Stage S200 Outputs Stage S100 The count pattern issuch that for the preclear condition stage S100 and stage S200 areplaced in the zero condition as illustrated in line 1 of the table. Thefirst count signal will cause the stages S100 and S200 both to take onthe one count condition as shown by line 2. Upon the occurrence of thesecond count signal the first stage S100 is returned to the zerocondition whereas the second stage S200 remains in the one condition asshown by line 3. A third input pulse as shown in line 4 causes stageS100 to return to its one condition and the stage S200 to return to thezero condition. The occurrence of the fourth count signal causes bothstages S100 and S200 to return to the zero condition. Thus it can beseen from an inspection of Table I that the counting pattern for stageS100 progresses according to the usual binary count pattern, that is, 01 0 1. However, the counting pattern for stage S200 does not. The stageS200, as is seen from the table counts 0 1 l 0 rather than the expectedpattern of O O 1 1. Thus, although four distinct count states exist,considering both stages S100 and S200, the count pattern is not thatnormally expected of a binary counting device. The counter, of the firstembodiment of FIGURE 3, may be used directly in that it provides signalsindicative of these four distinct states without any attempt toreconcile the actual count pattern with the usual count pattern for atwo stage binary device. The actual count pattern may be reconciled withthe usual count pattern by assigning the values 0, 1, 2 and 3arbitrarily to particular count patterns It should be understood, thatalthough only a two stage counting device is illustrated, the device maybe extended to any number of stages, each subsequent stage beingconstructed in the same manner as stage 5200, and

12 being connected to the previous stage in the manner of stage S200.

It should be noted that the output signals of stage 5100 and S200 asshown in Table I are the outputs of the B gates of substages S8102 andSS202 of stages S and S200 respectively. As stated above, the positivesignal represents the zero or reset condition whereas the negativesignal represents the one or set count condition. Thus, as shown inFIGURE 4, which illustrates the outputs of the gates of the stages S100and S200, the polarity of the output from the B gates may be readilyseen. Further, as indicated above with respect to the single stagedevice of FIGURE 1, both the B and B gates of each stage may be sensedsimultaneously to determine the stage output.

In order to permit counting according to the accepted binary countingpattern, a modification of the device as shown in FIGURE 3 may be made.This will permit the device to count according to the normally acceptedpattern, as described above. The output signals for the modified deviceof FIGURE 3 is shown in the table of FIGURE 5. The modification is shownin FIGURE 3 by means of dotted lines. It includes the use of a differentoutput line to conduct input signals to the second and all subsequentstages. The modified output line extends from the output of the B gateof substage SS104 of stage S100 rather than the B gate of substage S8102as was described in the first embodiment. The output line 60 conductsthe output of the output gate B to a terminal 62 which may alternativelybe connected to the switch blade 54 to conduct input signals to the line18 of the second and all subsequent stages. In addition, each stagebeyond the first will be modified by the addition of two diodes, afirst, diode A4, is added to the A gate of each subsequent stage. Inaddition, a further diode, U3, is added to the control section of eachsubsequent stage. These gates are effective during the preclearoperation to set up an initial signal pattern different than that whichis achieved in the first stage. In this manner the counting pattern ofall subsequent stages beyond the first may be caused to count accordingto the accepted binary pattern and thus produce a recognizable count.

As a result of the application of the positive preclear signal to thestages of the device, the first stage S100 will take on a patternsimilar to that described with reference to FIGURE 4. The second stage,S200, however, will take on a modified output pattern as illustrated inthe FIGURE 5 which describes the outputs of the various gates of stagesS100 and S200 in this modified arrangement. The positive preclear signalwill insure that the outputs of the gates A, B and C of stage S200 arenegative. Thus the inputs to gate A of stage S200 are all negativecausing the production of a positive output. The inputs of gate A are asfollows, diode Al has a negative input due to the negative output ofgate A of stage S200, diode A2 receives the negative output of gate B ofstage S100 and diode A3 receives the negative output of gate C of stageS200. The positive output of gate A of stage S200 is applied to diode A3of stage 5200 to control gate A to produce a negative output. As aresult of the application of the first input signal to stage S100 of thedevice a positive output will be generated by the gate B of stage S100and applied to the count signal line 18 of stage S200. This signal,however, will be inefiective to operate the substages of stage S200, inthat the positive signal applied to the diode A3, of the gate A by gateA of stage S200 prevents the device from responding to the input signal.Further, the positive signal applied to the diode A2 will cause the gateA to go to a negative value and apply negative signals to the diode B2.This, however, will not change the output of gate B and stage S200 willremain in the 0 count condition. This condition is indicated by theoutputs of the gates B of stage S100 and stage S200, which respectivelyproduce to stage S200.

"sections as was the substage of FIGURE 1. section of each of thesubstages consists of a gate A which operates as the input section; thesecond section is' known as the output section and consists of a gate Band '13 positive outputs indicative of the zero count. Upon receipt of asecond input pulse by the count signal line 18, the count device isplaced in the condition in which substage S8104 of stage S100 is made tocount and produces anoutput signal from its output section B over theline 60 to cause the second stage S200 of the device to count. The thirdinput pulse will cause the first stage S100 to return to the substageS5102 conducting and will not effect the stage S200 at all. When thefourth counting pulse arrives, it causes the substage S5104 of stageS100 to again conduct, an output will be produced which will effect thesecond stage S200. Therefore, normal manner of countingis achieved, thatis, that both stages will be placed inthe zero condition by the preclearsignal. The first input pulse will effect only the first stage S100,leaving the second stage S200 at zero, the second pulse, at which timethe first stage S100 is returned to the zero value, will cause thesecond stage S200 to be placed in the' one value; the third pulse willcause both stages S100 and-S200 to be placed intheir one value statesand finally, the fourth pulse will cause both stages to be returned tothe zero condition. Thus, with the modification of the device itispossible to make the count pattern produced that which is normallyacceptable for binary counting. Further, the count condition of thedevice may also be determined by sensing the outputs of the B and Bgates of each stagel Th'us the zero count may be indicated by thepositive outputof gate B and the negative output of gate Bwhich'together represent the zero count state of O l. The one count maybe represented as 1 by the negative and positive outputs of gates B andB respectively. FIG- URES 4 and 5 illustrate the outputs of the gates inthe counting device in the unmodified and modified conditionrespectively. A comparison of the two tables shows as for stageS100 thecounting pattern is the same in both embodiments. The counting pattern,however, for stage S200 has-been modified as shown-in FIGURE 5 as aresult of the additional preclear diodes and a different output positionof stage S100 used to supply input signals It should be understood thatas many stages as is desired may be employed,'each subsequent stageconstructed and connected as stage 2 of the counting device illustrated.The Table III indicates the count pattern achieved by'means of themodification:

Employing the principles taught with reference to the modulo 2 countingstage of FIGURE 1 a device for counting. in a modulo 3 number systemrnay be readily constructed. Reference is now made to FIGURE 6 where .isillustrated a single stage of a modulo 3 counting arrangementconstructed in accordance with the principles of this invention taken inconjunction with FIGURE 7 'which illustrates the outputs of the variousgates of the device. As can be seen from FIGURE 6, there are threesubstages, S8302, S8304 and S3306 which represent the first, second andthird substages of the stage shown. Each of the substages is constructedin three The first l B and C whereas the gates of the substage S8304 aredesignated A, B and C and finally, the gates of the .substage S3306 aredesignated A, B" and C. Each of the gates are constructed in a mannersimilar to that described with reference to FIGURE 1, namely a pluralityof diodes capable of accepting input and control signals as will bedescribed below at their anode connections. The cathodes of the gatediodes are connected in common through a resistance to a negativesupply. The cathodes are further connected to the base of a PNPtransistor connected in a grounded emitter configuration with thecollector connected via a resistor to a negative bias supply. The outputfrom each of the various gates is taken from the collector of the gatetransistor. The relative values of the bias voltages for the cathodes ofthe diodes and the collector of the transistor are again chosen so thatthe bias of the collector of the transistor is positive with respect tothe bias of the cathodes of the diodes of each of the gates. The gatesagain also of the negative input And-inverter type which producepositive outputs if all inputs are present and negative or a positiveoutput if any input is positive.

The gate A receives at diode A1 the output of the gate C of the substageS5302 via line 146, that is its associated control gate. Diode A2 issupplied with inputs from the count signal line 8 via the line 120.Diode A3 receives as an input the output of the gate A" via lines 170,172 and 174. Finally, the diode A4 receives as its input the output ofthe gate A via line 148. Gate B receives at diode B1 the output of gateA" via lines 170 and 172; at diode B2 the output of gate A via line 132;at diode B3, the output of gate B via line 176; and at diode E4 theoutput of gate B via line 126. The gate C receives as its inputs, atdiode C1 the output of gate B via line and at C2 the output of the gateA via line 128. As before, the gate C is made responsive to the inputand output sections of its associated substage.

The gate A receives as its A'1 diode the output of the gate C via line134; at diode A2 it receives the out put of gate A via line 132; atdiode A'3 is impressed the count signal from the count signal line 8 viathe line 122 and the diode A4 receives the output of the gate A vialines 170, 172 and 174. Gate B receives at diode B1 the output of gate Bvia lines 130 and 138; at diode B'2 the output of the gate A via line140; at diode B3 the output of the gate A via lines 124 and 178; atdiode B4 the output of the gate B" via line 176 and at diode B'S thepreclear pulse over the line 136. The gate C has the following inputs atits respective diodes: at diode C1: the output of the gate B via line142 and at diode C2 the output of the gate A via line 144.

Turning now to substage S8306 gate A", receives at diode A1 the outputof the gate C via line 180 at diode A2 the output of the gate A via line182; at diode A3 the output of gate A via line 132, and at diode A4 thecount signal from the count signal line 8 via the line 116. Gate Breceives at diode B"1'the output of the gate B via line 184; at diodeB"2 the output of gate A via line at diode B"3 the output of gate B vialine 138; at diode B4 is received the output of the gate A via line 186and at diode B5 the preclear signal on the line 136. Finally, thecontrol gate C of the substage S5306 receives at diode C1 the output ofthe gate B via line 188 and at diode C2 the output of the gate A vvialines 170 and 190.

Thus, it can be seen that the control gate of each stage is madedirectly responsive to the conditions of the input and output sectionsof their respective sulbstages and will produce a signal which is fed toits associated input section to control the response of the inputsection to count signals. The preclear signal on the line 136 operatesin a manner as described with reference to FIGURE 1, namely, the line ismade positive during the preclear period and is negative at all othertimes. Further, count signals on the count signal line are negativeduring the time the count signal is suplied and positive at all othertimes. The table of FIGURE 7 fully describes the manner of operation ofthe modulo 3 counting device of FIGURE 6. The outputs of the gates B ofsubstage 88304 and B" of substage 88306 are employed to produce theoutput indications for the stage. The reason for the use of the outputsof two gates rather than one as in preceding embodiments is that onegate output can only indicate a maximum of two conditions whereas twogate outputs can indicate a maximum of four conditions. Thus two gateoutputs are required to indicate the three possible count states of themodulo 3 count device of FIGURE 6. The outputs of gates B and B" areemployed to represent the count of zero. The 01 outputs of gates B and Bare used to represent the count of one and the outputs of these gatesare used as the two count Value. It should also be noted that withrespect to the modulo 3 count device a positive output will indicate aone whereas a negative output will represent a zero. Thus the countpattern as shown in FIGURE 7 is 00, 01, 10 and 00 for the clear, 1, 2,and 3 count signals.

It should also be noted that the count state of the device may also bedetermined by use of a single output from the counter with more involvedreadout sensing devices. If a positive output is the only one searchedfor and sampling gates are provided to determine for which substage thepositive signal originated the count state of the device may readily bedetermined. As can be seen from the table of FIGURE 7, gate B ofsubstage 88302 is the only output gate to produce a positive output as aresult of the preclear signal or in the period when the 3rd count signalterminates. Thus this output may indicate the zero count state. Gate B"of substage S8306 produces a positive output as a result of thetermination of the Ifirst count signal, thus its output may representthe one count condition. Finally gate B of substage 88304 produces apositive output as a result of the termination of the second count pulseand its output may be used to represent the second count state. Thus ifeach of the gates B, B and B" were connected to individual sensinggates, which were tested by three discrete sampling signals, it could bedetermined what the count state was depending upon which sampling signalcaused a signal to be passed through a sensing gate. Thus with morecomplex readout procedures, a single substage can be used to indicatethe count state of the device regardless of the number of substages.Further it is evident that the count state can readily be determined bytesting one less than the number of output gates available in a state,i.e. one output gate for a modulo 2 counting device and two output gatesfor a modulo 3 counting device. Additionally, all three output gatesignals may also be used to indicate the count condition of the modulo 3counting device by assigning certain output patterns arbitrary values.Thus the outputs of gates B, B and B of 100 may be assigned the zerovalue, outputs of 001 the one value and outputs of 010 the two value.The second count signal causes gates B and B" of substages 102 and 106to produce a negative signal and B a positive output.

Again, it can be seen, as was true of FIGURE 1, that the stage whosecontrol gate C produces a negative output prior to the count pulse willreceive the next count :signal. This is due to the operation of the gatein which :a negative signal operates as an alerting signal, and thepositive signal prohibits a gate from responding to a signal. As it willbe recalled, the reason for this is that the positive outputs of thecontrol gates will cause the input gates to produce negative outputsregardless of the type of signal impressed upon them by the count line.However, the single gate which receives the negative value from itscontrol gate is not so prohibited and its output will be determined bythe count signal impressed upon it from the input line 118. The entireoperation of the device is similar to that with reference to FIGURES 1and 2 and is summarized in the table of FIGURE 7. Hence the operationwill not be described in further .detail.

As was described with reference to FIGURES 3, 4

16 and 5, the industrial stages as shown in the FIGURE 6 may be combinedto produce a multi-stage asynchronous counting device operating in amodulo 3 numbering system. FIGURE 8 depicts a two-stage modulo 3counting arrangement. A first embodiment of the device which is a merecombination of two substages as shown in FIG- URE 6 is depicted entirelyin solid lines; An alternative arrangement of the device of FIGURE 8which will count according to normally accepted modulo 3 numberingsystem is also shown in FIGURE 8 by means of additional components andsignal transfer lines as indicated by the dashed lines and diodes. Thetable of FIGURE 9 describes in detail the manner of operation of thefirst embodiment of the FIGURE 8 Whereas the table of FIGURE 10describes the second arrangement or that arrangement shown with theadditional components. As was described in detail with reference to thecombination of two modulo 2 stages the counting arrangement providedthereby does not count according to the-normal modulo 3 countingarrangement, thus producing some variants to that normally accepted. Thecounting output is shown in pattern Table IV below.

Table of outputs for the substages of the first embodiment of FIGURE 8.

The above output pattern may be determined from an examination of theoutput gates B and B" of stages 8400 and 8500. The O0 outputs areindicative of the zero state, the 01 outputs indicate the one state andthe 10 outputs indicate the two state as was described with reference toFIGURE 7. As can be seen from the table of FIGURE 9, stage 8400indicates a normal counting pattern of 0, 1, 2; O, l, 2; O, 1, 2;however, stage S500 indicates a variation from the accepted pattern inthat it counts 0, 1, 1, 1; 2, 2, 2; O, O, 0. In this first embodiment,the count signals for the second and all further stages are provided bythe output of the output stage B of stage 88402 of stage 8400 via line250 terminal 252, switchblade 254 in the right contact position and line218. Thus, each time the counting sequence has caused the first substage88402 to produce in a negative output signal at the gate B a signal willbe presented to the second stage 8500 to cause its counting. Thus, inthat the first substage 88402 receives the first count pulse bothsubstage 88402 of the first stage 8400 and substage 88502 of the secondstage 8500 will be caused to count, causing an incorrect count whentested in view of the accepted manner of counting in modulo 3 numberingsystems.

It should be understood that the nine distinct inputs of the countingdevice of the first embodiment of FIG- URE 8 may be used directly orarbitrarily assigned values to permit a reconciliation between theactual outputs and the desired outputs as was described with referenceto FIGURES 3 and 4. Also the sensing gate arrangement described withreference to FIGURES 6 and 7 may also be employed to test for a positiveoutput value. The complete table of operation of this device is shown inFIGURE 9.

By a slight modification of the input arrangement for all subsequentcount stages beyond the first as shown in FIGURE 8, the device of thefirst embodiment may be made to count according to the normally acceptedmodulo 3 counting system. These modifications include a change of theinput line for all stages beyond the first whereby the input is takenfrom the output of gate B of the second substage S8504. This output isfed via line 260 terminal 262, the switchblade 254- in its leftmostposition to the count line'218 of stage 2 and all following stages. Thesecond substage and all subsequent stages have removed from them thediodes B'S and B"5 which are normally connected to the preclear line136. The switch 200 is conveniently, provided to permit thedisconnecting ofthe diodes B'Sand B"5 from the preclear line for thispurpose. In addition, a' diode A5 is added to the gate A of the substageS8402, as well as a diode A"5 added to the gate A. Both of these diodesreceive the preclear signal. In addition, the gate C is extended tothree diodes by the addition of a diode C'3 also connected at a preclearline. Under this condition, as in the modification described withreference to FIG- URES 6 and 7, the second and all subsequent substagesare prevented from counting in response to the first signal provided tothe counter, and permit the subsequent stages to count only once thepreceding stage has completed a full cycle of count and has produced anoutput. Thus, each time the counter arrives at the first substage afterthe first traversal of a full count cycle, a signal will be issued tothe count signal line 218 of the subsequent substages to permit them tocount.

The count pattern for the modified embodiment of FIGURE 8 is describedin Table V.

TABLE V Count Signal Stage 2 Stage 1 comqevmaswmro owmwt-w-n oooce oxiant-crev ce:

These outputs represent the outputs of gates B and B" of stages S400 andS500 as described with reference to FIGURE 9. The manner of operation ofthe device is similar to that described with reference to FIGURE 6 andis fully described with reference to FIGURE 10.

While only modulo 2 and modulo 3 single and multiple stage countingdevices are illustrated and described, it would be obvious to oneskilled in the art how the basic teachings of the invention may beextended to any modulo system for single count devices or multi-stagedevices. Futrher, it is understood that the multi-stage devices maybemade to contain as many stages as are necessary forv the particular useto which the device is to be put. V i p The embodiments of theinventionin which an exclusive property or privilege is claimed aredefined as followszr p I .1. An asynchronous counting device capable ofcounting according to a modulo three number system comprising: a first,a second and a third substage, each substage arranged to register adistinct one of the numbers of said modulo three number system, each ofsaid first, second and third substages further comprising an inputsection adapted to receive count pulses, an output section for providingan output signal in accordance with the count pulses received by saidinput section and a control section; three first means, each connectingthe control section of a single substage to the input section of thesame substage, to permit said control stage to control'the receipt ofcount pulses by said input section, a plurality of second means, eachconnecting the input and output sections of a single substage to thecontrol section of the same substage to actuate said control section inresponse to the condition of said input and output sections at thetermination of a count pulse; three third means, each interconnectingthe input sec-' tion of a single substage to the output section of thesame substage; and a plurality of fourth means interconnecting saidinput and output sections of all three of said substages to permit thereceipt of said counting pulses by said substages in a predeterminedsequence.

2. A device as claimed in claim 1, further comprising means to placesaid counting device in an initial condition prior to the receipt ofcount pulses.

3. An asynchronous counting device capable of counting according to amodulo three number system comprising: a first, second and a thirdsubstage, each of said first, second and third substages comprising aninput section adapted to receive count pulses, an output section forproviding an output signal in accordance with the count pulses receivedby said input section and a control section; three first means, eachconnecting the control section of a single substage to the input sectionof the same substage, to permit said control stage to control thereceipt of count pulses by said input section, a plurality of secondmeans, each connecting the input and output sections of a singlesubstage to the control section of the same substage to actuate saidcontrol section in response to the condition of said input and outputsections at the termination of a count pulse; three third means, eachinterconnecting the input section of a single substage to the outputsection of the same substage; a plurality of fourth meansinterconnecting said input and output sections of all three of saidsubstages to permit the receipt of said counting pulses by saidsubstages in a predetermined sequence; and output means connected to twoof the output sections of said first, second and third substages toproduce a signal indicative of the count in said counting device.

4. An asynchronous counting device capable of counting according to amodulo three number system comprising: a first, second and thirdsubstage, each of said three further comprising an input section adaptedto receive count pulses in a sequential manner from a common countsource, an output section for providing an output signal in accordancewith the count pulses received by said input section and a controlsection for controlling the receipt of count pulses by said inputsection; a plurality of first means, each connecting the control sectionof a single substage to the input section of the same substage to permitsaid control section to alert said input section and permit said inputsection to receive and count said count pulses, only one of said inputsections being alerted to receive a count pulse at any count pulse time;a plurality of second means, each connecting the input and outputsections of a single substage to the control section of the samesubstage to actuate'said control section in response to the condition ofsaid input and output sections at the termination of a count pulse; aplurality of third means, each interconnecting the input section of asingle substage to the output section of the same substage to cause saidoutput section to produce an output signal upon receipt by said inputsection of a count pulse; presetting means connected to said outputsections of said second and third substages to cause said output sectionto actuate its associated control section to prevent receipt by theinput sections of said second and third substages of the first countpulse and actuate said control section of said first substage to permitreceipt of said first count pulse by said input section of said firstsubstage; and a plurality of fourth means each interconnecting a singleoutput section with all of the remaining output sections of thesubstages, to pass the output signal of said single output section tosaid remaining output sections as well as to its associated con.- trolsection via said second means, to cause the control section of the nextsequential substage to alert its assoc ated input section and to causeall other control sections to prevent the receipt of the next countpulse by all other input sections, said alerting and preventing sequencecontinuing through said first, second and third substages for saidfirst, second and third counting pulses and then repeating for eachsuccessive group of three count pulses.

5. An asynchronous counting device capable of counting according to amodulo three number system comprising: a first, second and thirdsubstage, each of said three substages comprising an input sectionadapted to receive count pulses in a sequential manner from a commoncount source, an output section for providing an output signal inaccordance with the count pulses received by said input section and acontrol section for controlling the receipt of count pulses by saidinput section; a plurality of first means, each connecting the controlsection of a single substage to the input section of the same substageto permit said control section to alert said input section and permitsaid input section to receive and count said count pulses only one ofsaid input sections being alerted to receive a count pulse at any countpulse time; a plurality of second means, each connecting the input andoutput sections of a single substage to the control section of the samesubstage to actuate said control section in response to the condition ofsaid input and output sections at the termination of a count pulse; aplurality of third means, each interconnecting the input section of asingle substage to the output section of the same substage to cause saidoutput section to produce an output signal upon receipt by said inputsection of a count pulse; presetting means connected to said outputsections of said second and third substages to cause said output sectionto actuate its associated control section to prevent receipt by theinput sections of said second and third substages of the first countpulse and actuate said control section of said first substage to permitreceipt of said first count pulse by said input section of said firstsubstage; a plurality of fourth means each interconnecting a singleoutput section with all of the remaining output sections of thesubstages, to pass the output signal of said single output section tosaid remaining output sections as Well as to its associated controlsection via said second means, to cause the control section of the nextsequential substage to alert its associated input section and to causeall other control sections to prevent the receipt of the next countpulse by all other input sections, said alerting and preventing sequencecontinuing through said first, second and third substages for saidfirst, second and third counting pulses and then repeating for eachsuccessive group of three count pulses; and output means connected totwo of the output sections of said first, second and third su'bstages toproduce a signal indicative of the count in said counting devices.

6. A multi-stage asynchronous counting device capable of countingaccording to a modulo three number system comprising: a plurality ofcounting stages, each stage registering the counts within a distinctorder of said number system, each of said stages composed of a first,sec-- ber system, each of said substages further comprising an inputsection adapted to receive count pulses in a sequential manner from acommon count line, an output section for producing an output signal inaccordance With the count pulses received by said input section and acontrol section for controlling the receipt of count pulses by saidinput section; a plurality of first means, each connecting the controlsection of a single substage to the input section of the same substageto permit said control section to alert said input section and permitsaid input section to receive and count said count pulses, only one ofsaid input sections being alerted to receive a count pulse at any countpulse time; a plurality of second means, each connecting the input andoutput sections of a single substage to the control section of the samesubstage to actuate said control section in response to the condition ofsaid input and output sections at the termination of a count pulse; aplurality of third means, each interconnecting the input section of asingle substage'to the output section of the same substage to cause saidoutput section to produce an output signal upon receipt by said inputsection of a count pulse; a plurality of fourth means eachinterconnecting said input and output sections of the substages of asingle stage to permit the receipt of said counting pulses by saidfirst, second and third substages in a predetermined sequence; aplurality of fifth means each connecting a predetermined output sectionof one of said substages of a stage to the common count line of thefollowing stage; a sixth means connecting the common count line of thefirst stage to a source of count pulses, whereby said first stagereceives count pulses and each succeeding stage receives a pulse eachtime the previous stage receives three pulses; and presetting meansconnected to each stage of said counting device to place said countingdevice in an initial condition prior to the receipt of count pulses.

7. A multi-stage asynchronous counting device capable of countingaccording to a modulo three number system comprising: a plurality ofcounting stages, each stage registering the counts within a distinctorder of said number system, each of said stages composed of a first,second and third substage, each of said substages comprising an inputsection adapted to receive count pulses in a sequential manner from acommon count line, an output section for producing an output signal inaccordance with the count pulses received by said input section and acontrol section for controlling the receipt of count pulses by saidinput section; a plurality of first means, each connecting the controlsection of a single substage to the input section of the same substageto permit said control section to alert said input section and permitsaid input section to receive and count said count pulses, only one ofsaid input sections being alerted to receive a count pulse at any countpulse time; a plurality of second means, each connecting the input andoutput sections of a single substage to the control section of the samesubstage to actuate said control section in response to the condition ofsaid input and output sections at the termination of a count pulse; aplurality of third means, each interconnecting the input section of asingle substage to the output section of the same substage to cause saidoutput section to produce an output signal upon receipt by said inputsection of a count pulse; a plurality of fourth means eachinterconnecting said input and output sections of the substages of asingle stage to permit the receipt of said counting pulses by saidfirst, second and third substages in a predetermined sequence; aplurality of fifth means each connecting a predetermined output sectionof one of said substages of a stage to the common count line of thefollowing stage; a sixth means connecting the common count line of thefirst stage to a source of count pulses, whereby said first stagereceives count pulses and each succeeding stage receives a pulse eachtime the previous stage receives three pulses; presetting meansconnected to each stage of said counting device to place said countingdevice in an initial condition prior to the receipt of count pulses; anda plurality of output means,

each connected to two of the output sections of said first, second andthird substages of each stage to produce a signal indicative of thecount in said counting device.

8. A multi-stage asynchronous counting device capable of countingaccording to a modulo three number system comprising: a plurality ofcounting stages, each stage registering the counts within a distinctorder of said number system, each of said stages composed of a first,second and third substage, each substage arranged to register a distinctone of the numbers of said modulo three number system, each of saidsubstages further comprising an input section adapted to receive countpulses in a sequential manner from a common count line, an outputsection for producing an output signal in accordance with the countpulses received by said input section and a control section forcontrolling the receipt of count pulses by said input section; aplurality of first means, each connecting the control section of asingle substage to the input section of the same substage to perunitsaid control section to alert said input section and permit said inputsection to receive and count said count pulses, only one of said inputsections being alerted to receive a count pulse at any count pulse time;a plurality of second means, each connecting the input and outputsections of a single substage to the control section of the samesubstage to actuate said control section in response to the condition ofsaid input and output sections at the termination of a count pulse, aplurality of third means, each interconnecting the input section of asingle substage to the output section of the same substage to cause saidoutput section to produce an output signal upon receipt by said inputsection of a count pulse; presetting means connected to the outputsections of said second and third substages of each stage to permit saidfirst substage to receive the first count pulse; a plurality of fourthmeans each connecting the output sections of the substages of a singlestage, to permit the passage of the output signal produced by the outputsection of said first stage, as a result of the receipt of the firstcount pulse by the input section of said first stage, to said second andthird substages to permit said second substage to receive the secondcount pulse and prevent said third substage from receiving said secondcount pulse; said output of said output section of said first substagein response to said first count pulse further being passed via saidsecond means to the control section of said first substage to preventsaid input section of said first substage from receiving said secondcount pulse; a plurality of fifth means each connecting the outputsections of the substages of a single stage to permit the passage of theoutput signal produced by the output section of said second substage, asa result of the receipt of said second count pulse by the input sectionof said second substage, to said first and third substages to permitsaid third substage to receive the third count pulse and to prevent saidfirst substage from receiving said third count pulse; said output ofsaid output section of said second substage, as a result of the receiptof said second count pulse, further being passed via said second meansto the control section of said second substage to prevent the receipt bysaid input section of said second substage of said third count pulse; aplurality of sixth means each connecting the output sections of thesubstages of a single stage to permit the passage of the output signalproduced by the output section of said third substage as a result of thereceipt of said third count pulse by the input section of said thirdsubstage, to said first and second substages to permit said firstsubstage to receive the fourth count pulse and to prevent the sec-ondsubstage from receiving said fourth count pulse; said output of saidoutput section of said third substage, as a result of the receipt ofsaid third count pulse, further being passed via said second means tothe control section of said third substage to prevent the receipt bysaid input section of said third substage of said fourth count pulse;said alternate control of said input sections continuing on allsuccessive count pulses to permit said first substage to receive thefirst count pulse of each three count group, said second substage toreceive the second count pulse of each three count pulse group, and saidthird substage to receive the third count pulse of each three countpulse group; a plurality of seventh means each connecting the outputsection of the first substage of a stage to the common count line of thenext succeeding stage; and an eighth means connecting the common countline of the first stage to a source of count pulses, whereby said firststage receives count pulses and each succeeding stage receives a pulseeach time the previous stage receives a count pulse at its firstsubstage.

9. A multi-stage asynchronous counting device capa V ble of countingaccording to a modulo three number system comprising: a plurality ofcounting stages, each stage registering the counts within a distinctorder of said number system, each of said stages composed of a first,second and third substage, each substage arranged to register a distinctone of the numbers of said modulo three number system, each of saidsubstages further comprising an input section adapted to receive countpulses in a sequential manner from a common count line,

an output section for producing an output signal in accordance with thecount pulses received by said input section and a control section forcontrolling the receipt of count pulses by said input section; aplurality of first means, each connecting the control section of asingle substage to the input section of the same substage to permit saidcontrol section to alert said input section and permit said inputsection to receive and count said count pulses, only one of said inputsections being alerted to receive a count pulse at any count pulse time;a plurality of second means, each connecting the input and outputsections of a single substage to the control section of the samesubstage to actuate said control section in response to the condition ofsaid input and output sections at the termination of a count pulse, aplurality of third means, each interconnecting the input section of asingle substage to the output section of the same substage to cause saidoutput section to produce an output signal upon receipt by said inputsection of a count pulse; :a plurality of fourth means each connectingthe output sections of the substages of a single stage, to permit thepassage of the output signal produced by the output section of saidfirst stage, as a result of the receipt of the first count pulse by theinput section of said first stage, to said second and third substages topermit said second substage to receive the second count pulse andprevent said third substage from receiving said second count pulse; saidoutput of said output section of said first substage in response to saidfirst count pulse further being passed via said second means to thecontrol section of said first substage to prevent said input section ofsaid first substage from receiving said second count pulse; a pluralityof fifth means each connecting the output sections of the substages of asingle stage to permit the passage of the output signal produced by theoutput setcion of said second substage, as a result of the receipt ofsaid second count pulse by the input section of said second substage, tosaid first and third substages to permit said third substage to receivethe third count pulse and to prevent said first substage from receivingsaid third count pulse; said output of said output section of saidsecond substage, as a result of the receipt of said second count pulse,further being passed via said second means to the control section ofsaid second substage to prevent the receipt by said input section ofsaid second substage of said third count pulse; a plurality of sixthmeans each connecting the output sections of the substages of a singlestage to permit the passage of the output signal produced by the outputsection of said third substage, as a result of the receipt of said thirdcount pulse by the input section of said third substage, to said firstand first substages to permit said first substage to receive the fourthcount pulse and to prevent the second substage from receiving saidfourth count pulse; said output of said output section of said thirdsubstage, as a result of the receipt of said third count pulse, furtherbeing passed via said second means to the control section of said thirdsubstage to prevent the receipt by said input section of said thirdsubstage of said fourth count pulse; said alternate control of saidinput sections continuing on all successive count pulses to permit saidfirst substage to receive the first count pulse of each three countpulse group, said second substage to receive the second count pulse ofeach three count pulse group, and said third substage to receive thethird count pulse of each three count pulse groups; first presettingmeans connected to the output sections of said second and thirdsubstages of the first stage to permit the first substage to receive thefirst count pulse; second presetting means connected to the inputsections of the first and third substages and the control section ofsaid second substage of all succeeding stages to alter the sequence ofreceipt of count pulses by said substages of a stage to permit saidfirst substage -to receive the first pulse of each three count pulsegroup, said second substage to receive the second pulse of each threecount pulse group and the third substage to receive the third pulse ofeach three count pulse group a plurality of seventh means eachconnecting the output section of the second substage of a stage to thecommon count line of the next succeeding stage; and an eighth meansconnecting the common count line of the first stage to a source of countpulses, whereby said first stage receives count pulses and eachsucceeding 24 stage receives a pulse each time the previous stagereceives a count pulse at its first substage.

References Cited by the Examiner UNITED STATES PATENTS 3,114,883 12/1963Arthur 23592 3,218,483 11/1965 Claffer 30788.5

FOREIGN PATENTS 845,371 12/ 1960 Great Britain,

1. AN ASYNCHRONOUS COUNTING DEVICE CAPABLE OF COUNTING ACCORDING TO AMODULO THREE NUMBER SYSTEM COMPRISING: A FIRST, A SECOND AND A THIRDSUBSTAGE, EACH SUBSTAGE ARRANGED TO REGISTER A DISTINCT ONE OF THENUMBERS OF SAID MODULO THREE NUMBER SYSTEM, EACH OF SAID FIRST, SECONDAND THIRD SUBSTAGES FURTHER COMPRISING AN INPUT SECTION ADAPTED TORECEIVE COUNT PULSES, AN OUTPUT SECTION FOR PROVIDING AN OUTPUT SIGNALIN ACCORDANCE WITH THE COUNT PULSES RECEIVED BY SAID INPUT SECTION AND ACONTROL SECTION; THREE FIRST MEANS, EACH CONNECTING THE CONTROL SECTIONOF A SINGLE SUBSTAGE TO THE INPUT SECTION OF THE SAME SUBSTAGE, TOPERMIT SAID CONTROL STAGE TO CONTROL THE RECEIPT OF COUNT PULSES BY SAIDINPUT SECTION, A PLURALITY OF SECOND MEANS, EACH CONNECTING THE INPUTAND OUTPUT SECTIONS OF A SINGLE SUBSTAGE TO THE CONTROL SECTION OF THESAME SUBSTAGE TO ACTUATE SAID CONTROL SECTION IN RESPONSE TO THECONDITION OF SAID INPUT AND OUTPUT SECTIONS AT THE TERMINATION OF ACOUNT PULSE; THREE THIRD MEANS, EACH INTERCONNECTING THE INPUT SECTIONOF A SINGLE SUBSTAGE TO THE OUTPUT SECTION OF THE SAME SUBSTAGE; AND APLURALITY OF FOURTH MEANS INTERCONNECTING SAID INPUT AND OUTPUT SECTIONSOF ALL THREE OF SAID SUBSTAGES TO PERMIT THE RECEIPT OF SAID COUNTINGPULSES BY SAID SUBSTAGES IN A PREDETERMINED SEQUENCE.